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ccir generator
Hi!
I am also interested in CCIR601/656 generator IP core for FPGA (or digital RGB to CCIR601/656 converter). For moment, try AD7181 chip
Hi friend!
I have the same problem with a microwave tube made by THOMSON VARIAN ( in France) a red painted microwave tube marked TV 220.
I also think this is a klystron , but no datasheet , no info at all found on the internet. Can you help me ?
Regards,
s1sar1
SuSE Linux 8.0 a good environment for EDA tools
Installed IC 5.0 an works fine ( 8 or 24 bit color mode ). SuSE 8.0 works fine with hardware (lot of good drivers compared to RedHat 8.0 or 7.2)
With Modelsim or Synopsys ..no problem ! ;-)
Only Hspice linux version still not work on SuSE ...
vhdl ams products
Hi!
What about Mentor Sy$tem Vision VHDL-AMS simulators??. It also can use SPICE files and has a very nice interface.
Other good VHDL-AMS sim are:
- Smash ( www.dolphin.fr )
- Saber De$igner ( now Synop$ys propery ) uses MAST language, pretty
close to VHDL -AMS.
Modelsim vs. Active HDL
I think with Modelsim you can do pre and post synthesis simulations (even post-layout) because it allows SDF backannotation.
Active HDL doesn't have this but is better for code-writing than Modelsim
(templates, a more easy to use interface).
sdf negative timing
After synthesizing a VHDL design with Synopsys DC I get negative values
in the SDF file for HOLD check of the FFs . I am doing simulations with Modelsim and the simulator uses those negative HOLD values by substracting them from the setup time ( If i deliberately make a...
flexlm hostid linux
BTW gus, do you know that on some Intel815 boards equiped with
3com 3C920 onboard ethernet controllers you can permanently change
the MAC adress (host-ID) even in Windows ?
With Configure/Advanced/Network Adress things are quite easy ;)
I noticed important timing modifications in writing the SDF file with DC and with Primetime. Which of them gets the best (and right) timing results good for a simulation? (i am using the 2000.11 DC&PT version and TSMC0.25 libs)
I am newbie in ASIC design and want to ask what does a negative setup
or hold timecheck in an DC generated SDF file means. I need some help
in understanding the SDF for sequencial components.
Hy all,
Did anybody try some simple adaptive algorithms implementation(like LMS) in an XilinxFPGA before?
What about new Xilinx&Mathworks alliance which release System Generator software, did anybody try it?
It is VHDL code generated from Simulink ,really optimal or not?
Thanks for answering...
Hi friend!
Yes, S@ber Designer has features included for optical systems simulation with quite good accuracy! Also you can find optical devices models written in MAST (a kind of VHDL-AMS)
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