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1qn 2qn cordic
I'll appriciate if smbd helps me by VHDL text to convert data in range
-2^N ...+2^N to 1QN and 2QN codes in range -1...(1-2^-N) and reverse to implement XILINX CORDIC IP.
Can I add some instruction or option to define specific FPGA (CPLD)device in my project. My Customer is given 'edif' or 'tdo' files for further sinthesis. I do not want him to implement another device except specified one for compilation. How to protect my design?
8O
parallel divide vhdl
Dear friends. I'll appriciate if smbd sends me VHDL text for parallel division algorithm in VHDL. I need to divide exmpl 22 bits word by 12 bits word. I made the same in Altera LPM_DIVIDE. Now I have similar task in XILINX ISE WebPack. Thanks all in advance.:)
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