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Recent content by sindrig

  1. S

    2's complement in verilog

    Hi, I figured that out just before your post. I've also looked over your link and will try to implement something from it into my project. But have you got an idea for why my sum now (see above) becomes the 2's complement of B? Best regards, Sindri
  2. S

    2's complement in verilog

    Hey guys, I have this project for school and i'm getting really frustrated with it. I'm supposed to create a circuit that can add or reduct one 4-bit number from another using full-adders that use half-adders. I've managed to make it work with addition but reduction's a bit more complicated. I...

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