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Should I simulate it with a baud rate 115.2k in the testbench or ?
I'll show you the simulation below. the simulation is also included inside of the project files in zip as attachment.
`timescale 1ns / 1ps
module uart_rx_TB ();
// We downscale the values in the simulation
// this will...
I have an additional question if possible,
The uart module isn't working as expected. This is what it looks like inside of a simulation for the transmission of byte. This looks normal to me, so I was wondering where the issue could be and was hoping to get some help on that if possible.
Here...
Solved... For some strange reason it works now. I had changed the non-blocking assignments yesterday as well but it was still showing me latches, now not anymore..
Hey, yes I did that as I saw the issue after posting, but no luck. to be more specific from in the SDONE state, I made the assignments from non-blocking to blocking is what I mean.
Hey,
I was wondering if I could get some help on the following issue.
I am getting latches for the registers shown in the picture and I can't figurer out why that is the case. It is a uart_rx module with an FSM. When determining the next state logic it is telling me that I am receiving...
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