Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Simon_Chueh

  1. S

    FFT plot of CT-Delta Sigma ADC which cannot be explained

    If it is the stability probelm, why only in-band noise is different? High frequency noise remain same. I ruled out the problem of loop-filter due to these reasons; however, I am not 100% sure about it. Yes, I do compensate ELD. ELD is set to be half of clock cycle, which is realized by...
  2. S

    FFT plot of CT-Delta Sigma ADC which cannot be explained

    Hello all, I am designing a CT-Delta Sigma ADC. The spec of this ADC is: 3rd-order, 4-bit Quantizer, Fs=320MHz, OSR=16, BW=10MHz, CIFF structure The problem I encountered is some strange result from the FFT of the ADC. Attached figure is 5 different input bin; from low frequency to high...

Part and Inventory Search

Back
Top