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jobs in vlsi, usa
I think the US vlsi market is selectively good and bad.
Intel is hiring many people in the consumer electronic group.
The best requirement is some years of experience with a master degree.
Hope all you have a good job.
Dear all,
Xilinx advertizement or datasheet says about the size of FPGA as System Gate.
Does anyone know how to come up with the calculation of the system gate?
The largest Virtex-II XC2V8000 is about 8 M sytem gates.
Does this mean I can implement 8M logic gates? I guess this is definitely not...
sdf modelsim
In Xilinx ISE 5.1i, double-click on "Generate Post-place & route simulation model". This will generate the sdf and vhdl for Modelsim.
simon2kk
For Virtex-II pro development, you need EDK (embedded development kit).
Virtex-II pro developer's kit (a.k.a VDK) is included in EDK.
System generator for PowerPC beta version is also included in EDK.
EDK5.1 also includes ISE 5.1 evaluation version.
To run EDK, you need to have ISE5.1.
Thus...
I was reading some DSP books and wonder how floating point algorithm is converted to a fixed point algorithm. I guess the blind conversion will cause the quantization plus lots of overflow problem.
Is there any formal or common method that determines the precision that minimize the errors.
I am...
I understand that we can use "load enable" kind of control instead of clock gating.
I wonder if both techniques use the same power consumption.
Anyone has an experience on this?
wlf file currently in use
I think if you just delete the vsim.wlf file, then you will be ok.
I think it happened when modelsim dies without proper closing process.
I recommand the book, VHDL by Ben Cohen.
It seems to me that the book explains more friendly on Vhdl.
It is good if you read along with Ashedan's book.
That is how I did it.
In V-II Pro developer's kit, there are three reference designs that use powerpc and fpga together.
You can simulate them with Modelsim and make the last bitstream file.
In these ref, small codes are located in Block RAM and the powerpc starts reading and executing the code.
If you want to use...
fpga cheap
If you go to Xilinx website and search "development board",
you can get some results.
Spartan FPGA based boards are pretty cheap (not sure how much is cheap, however).
Hello, mami_hacky.
I did not answer your question.
Regarding the question whether you have to use CoreConnect or not,
it is up to you.
CoreConnect is the optional bus for PowerPC and Microblaze.
If you need your own bus, you can design and use it on V-IIpro.
Of course, it is much easier to...
CoreConnect is the bus standard from IBM.
In Xilinx tool, it is designed as Soft IP which means that it uses the CLB (or Slice in Virtex-II pro) on FPGA.
You can instantiate and simulate it for PowerPC core or MicroBlaze processors.
simon2k
One interesting device is Actel ProASIC plus.
It is FlashMemory based FPGA not SRAM based. Once you set the configuration and use FlashLock, no one can read out the configuration.
You also don't need other extra battery to keep the protection.
As far as I know, the simulation for the embedded PowerPC core can be done using Virtex-II pro developer's kit.
It includes the swift model for the PowerPC and associated gnu gcc compiler.
You can simulate using Modelsim.
But, Xilinx is still developing the tool and is in alpha version.
Simon2kk
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