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Recent content by simon110

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    Help:how to evaluate the performance of SHA in ADC?

    Hi wan 1."You are right, the spectrum will overlapp when input frequency exceed Nyquist frequency. But, SINAD of a well-designed ADC will drop slowly even when input frequecy exceed. We can see that in some papers and PHD thesis from UCB" I think you should examine the SFDR and THD when you...
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    Help:how to evaluate the performance of SHA in ADC?

    Hi,TiwstedNeurons For a 10bit 80M adc. How about if I caculate the settling time limitation in this way(assume half-cycle ): 2^10=1024 ---> 1/(2fs)<7tau -----> tau< 1/(14fs) ------> tau< 3.57 ns So would you please let me know how you get 5.5 ns? thx 1. 5.5ns is not calculated by me...
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    [req]EE240 course lecture from berkeley

    hi, Bharath The link I provided is available now. and I have tested the link before providing it. it's not my fault if you can't open it!
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    need help in folded cascode design

    eecs240 **broken link removed**
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    some problems about pipeline ADC

    if you simulate the S/H in pipeline adc, I think you should include the capacitance of SC-CMFB and the input capacitance of comparator,so CL=Cnext+Ccom+Cout+Ccmfb+Ceff Cnext:the sample capacitor of next stage Ccom:the capacitance of comparator Ccmfb: the capacitance of SC-CMFB Ceff...
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    [req]EE240 course lecture from berkeley

    **broken link removed**
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    Recommendation for op-amp?

    telescopic gain boosted op amp is a good choice, you can read some book such as analysis and design of analog integrated circuit 4th edition P.R.Gray, in additon, some final reports of EECS 240 are practical
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    Help:how to evaluate the performance of SHA in ADC?

    you can do trans simulation and take fft. when you do trans simulation, you can find some information such as settling time.for example, a 10bit 80M pipeline adc, the settling time should be not more than 5.5ns(exclude the nonoverlap time), as for the dynamic specification, the most important...

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