Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I am trying to simulate Ternary SRAM cell. which can memorize logic 0,1,2 or in vtg level as 0v,1.5v,3v. I want to find simulation result for SNM of the ternary SRAM.
Please help.
SRAM cell SCHEMATIC
Thanks in advance.
regards,
Siddharth
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
