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Recent content by sid_27

  1. S

    Why are ADC's output in 2'complement

    My quesion is why are all ADC's output are in 2'complement. I am using LTC2294 ADC it gives output in offset binary or 2'complement, what is the reason behind this. Can I use 2'complement data stright away in my VHDL code or I have to convert it back to simple binary and then use it in my code...
  2. S

    Generating a pulse of 100ns

    On every CLK event the Old value of R.H.S gets assigned to L.H.S, Hence in this case on the 5th CLK U will get Logic '1' at the O/P.
  3. S

    Generating a pulse of 100ns

    Try The Following Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PULSE is Port ( CLK : in STD_LOGIC; RST_PULSE : out STD_LOGIC); end PULSE; architecture Behavioral of PULSE is signal rst1, rst2, rst3, rst4, rst5 : std_logic:='0'; begin process(CLK) begin...
  4. S

    5:2 Compressor Block Diagram & Truth Table

    Hi Guys! Here is a link to a online arithmetic core generator which can generate a structural HDL code for several arithmetic operation: http://www.ellab.physics.upatras.gr/~bakalis/Eudoxus/ regards
  5. S

    Error: Clock tree synthesis in Encounter 10.1

    I guess this question is related to ASIC if I am not wrong, You should post this question in the other forum named: ASIC Design Methodologies and Tools (Digital). You could get help more quickly. Regards
  6. S

    5:2 Compressor Block Diagram & Truth Table

    My bad, I forgot to mention that I was also doing the research parallelly my apologies for that. Suerly I will post the resources I am refering and ask for your help if I got stuck, and the code too if anyboady requiers it, onces its done. Regards
  7. S

    Easy question about pipeline: Is this code synthesizable?

    I feel there is no need of for loop here. If you want to do the temp1, temp2, result multiplication sequentially using case why need for loop simply use a counter to increment "i". Regards
  8. S

    5:2 Compressor Block Diagram & Truth Table

    Hi ads-ee, Thanks for your efforts, really appretiate it. The papers you shared I already have it. I found couple of papers myself which I think will do my work: https://www.mattkeeter.com/research/jackson.pdf, https://www.iis.ee.ethz.ch/~zimmi/publications/adder_arch.pdf. These two pdfs will...
  9. S

    5:2 Compressor Block Diagram & Truth Table

    Hi ads-ee, Thanks for your advice really appreciate it....! Well I searched a lot on google but all I got was 16-bit Sklansky adder graph representation, The only reason I post this on this form was, I thought if anyboady has already worked on this he/she can help me with the schematic so that I...
  10. S

    Need some Advice in VHDL

    Hi, use FSM it's good idea but as told KlausST , i should at first stop all operations till input data are changed , but use some thing to compare input data , but how i can compare input data for before and after first result ? Can U elaborate what exactly your design is, what are the inputs...
  11. S

    Need some Advice in VHDL

    Hi, Design/Write a state-machine that will control this operation. As Klaus suggested generate some flags with this FSM which control this operation.
  12. S

    5:2 Compressor Block Diagram & Truth Table

    Hi ads-ee, Thanks for the help. I want to design wallace tree multiplyer using 5:2 compressor and Sklansky adder. I wan to design 16x16bit multiplyer for that I need 32-bit sklansky adder. Please can anybody provide me with "Graph representation of 32-bit Sklansky adder"
  13. S

    What is Emulation work in Industrty?

    An emulation engg does ASIC prototyping on emulator which contains multiple FPGAs, which enables fast and accurate system modeling and verification.
  14. S

    5:2 Compressor Block Diagram & Truth Table

    Hi, Please can any one help me with the 5:2 compressor block diagram, there are many available on net:roll: but none of them is in detail:thumbsdown:, Like they dosenot show which output in the XOR-XNOR block is XOR n which is XNOR, the same goes with the MUX block to, not able to identify...
  15. S

    How to determine frame rate from pixel clock

    What is the formula to calculate the fps, If my VGA Controller is 1024x768 and pixel clock is 65 MHz. What adjustment i have to do if I want 30fps output.
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