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Recent content by shyla

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    [SOLVED] what is clock latency and clock uncertainty

    what is clock latency Clock Latency is the delay in the clock signal from the clock source port to any clock pin in the circuit. Clock uncertainity is jitter. But jitter and skew are two different terms. Jitter is the variation in the clock period ( that is the clock edge might not be at the...
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    What type of constraints apply for routing?

    Routing The basic constraint is DRC, LVS, Timing, Crosstalk issues. It depends on what routing you are doing. If it is a power routing, then there are few other things like EM/IR issues that has to be taken care of. If it is clock routing, then double spacing and shielding for high frequency...
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    Meeting timing but not target skew value

    skew and timing Meeting the skew target is dependent on the design requirement.
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    Can we add a delay buffer on the clk capture path to reduce the setup slack value?

    setup slack Hi, Buffer addition to the capture clock path will definately help to improve the setup slack. But we need to be careful as it can violate hold at that point as we are delaying the capture clock. This methodology can be tried if the hold numbers are positive. Make sure that you add...
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    Tcl and Perl for backend VLSI design

    tcl or perl According to me, most of the Physical Design reated scripts are programmed using TCL and the wrappers to these scripts are written using Perl. So to master in backend, Tcl and Perl are equally important.
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    PrimeTime Timing Closure

    timing closure Hi, Can anyone please explain me regarding the differences between timing analysis in PrimeTime using SPEF and SDF? How is the timing analysis using SDF different from timing analysis using SPEF and which one is better? Regards, Shyamala
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