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Hi
Given multiple mux choices(2:1, 4:1, 8:1,10:1 muxes), how do you design a 40:1 clock mux for low power?
There is no limit to the the number of the standard muxes you can choose.
Thanks
cadence 2nd order harmonic
hi
i am attaching a doc on thd simulations
a very good reference..detailed step by step procedure given along with explanations
shweta
Re: layout R,L,C
hey
just in case u still need the info abt how to layout RLCs
(or may be can be useful for someone else)
here it is
i have used cadence virtuoso for doing layouts
Layout of Resistance:
for resistance, we can use
1. poly or
2. pwell
to layout.
to start off draw a...
for the cascode current mirror, the compliance voltage is 2vdsat + vth!!!the bottom transistor requires vdsat+vth for it to be in saturation and the top transistor therefore requires vdsat+vdsat+vth.
can someone clearly explain the derivation of compliance voltage for the self regulated current...
i know the output impedance of the self regulated is more than the cascode current mirror..what i want to know is in which case the compliance voltage is less?compliance voltage i mean, the minimum voltage needed to keep the config in saturation mode and thereby make it work as current mirror...
hi all
among the cascode and self regulated current mirror(in which the source voltage of the top transistor is amplified and supplied as the gate voltage to the same transistor), which one has better(less) compliance voltage and why?
thanks in advance!
-shweta
Hi
You are right!!
|-> means both the triggering condition and fulfilling condition must be true in the same sample.
|=> means if the triggering condition is true,then the fulfilling condition must be true in the next sample.
For example:
@(posedge clk) a |-> b
Here if a (triggering...
system verilog books
Hi
SystemVerilog for Verification by Chris Spear is good to start with.
Also,you can visit www.sutherland-hdl.com and www.suburst-design.com for
papers/presentations on SystemVerilog.
Hope this information is useful to you
Shweta
Re: perl
Learning Perl by O'Reilly is good to start with.
Here is the link for e-book
h**p://www.unix.org.ua/orelly/perl/index.htm
You can find many advance level books also here!!
Also perl software is available for free.
For level-sensitive storage element such as latch, data must arrive a certain minimum time befor clock goes inactive. A setup violation can cause invalid data to be captured by the latch or other level-sensitive device.
Hold time is the time for which the data for the next clock cycle shouldnot...
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