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Recent content by shrikantec

  1. S

    final sign off of STA flattening or hierarchical netlist is prefered ?

    final sign off of STA flattening or hierarchical netlist is prefered ?
  2. S

    what is latchup ? and body effect ? in CMOS.....

    what is latchup ? and body effect ? in CMOS.....
  3. S

    PD engineer CV for freshers entry

    hi, i have completed PD course using Cadence Soc encouter and i am looking for job. if any one have the PD engineer CV for freshers. kindly send the same.what are things need to put in the CV.
  4. S

    what is routing? types of routing? when can we say.. it s good routing?

    what is routing? types of routing? when can we say.. it s good routing?
  5. S

    what is useful skew ?

    what is useful skew ?
  6. S

    What is cross talk ?

    What is cross talk? How can you avoid? in which stage this problem will come and in which stage need close the issue.
  7. S

    What is antenna effect?

    What is antenna effect? in which stage this problem will come and in which stage need close the issue.
  8. S

    Which layer is used for clock routing and why?

    Which layer is used for clock routing and why?
  9. S

    What is EM and it effects?

    What is EM and it effects? in which stage this problem will come and in which stage need close the issue.
  10. S

    What is IR drop? How to avoid .how it affects timing?

    What is IR drop? How to avoid .how it affects timing? in which stage this problem will come and in which stage need close the issue.
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