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Recent content by shobhitk

  1. S

    $period( ) Timming check Error Modelsim

    Hi Guys I am using Model sim for my SOC , as well as we have RTL Simulations,Worst Case Simulations and Best Case Gate Simulations while worst case simultaion is passed without errors but Best Case is showing some missmatches which contains ** Error...
  2. S

    Question of passing a signal between 2 clock domain

    handshaking is good option or we can have mux based syncronizers
  3. S

    schematic generation with design vision

    Yes it is possible
  4. S

    the vhdl code for the video processing

    images on hdl In my previous method I used perl model for converting real image but its was in ppm format
  5. S

    What is Verification Plan and Test Plan.........?

    But I think Verification plan is for whole system verification and Test Plan is for specific tests just like FIFO , Registers , Path and all.we can say that testplans are subset of Verification plan
  6. S

    Spyglass Querry :: Message ( Warning and Info export querry)

    is it the method ? Select All Message and Copy the Them. Paste into any file on GVIM/Emacs and Save As: .csv file not make that file back to windows then open then in excel
  7. S

    How to compile VHDL files that are below the Verilog at the top level using VCS MX?

    vcs mx I am not very shure .... but there is a command +vhdlan and few more to run that command.I used that couple of years back . I will let you know very soon thanks for reminding me :-)
  8. S

    Spyglass Querry :: Message ( Warning and Info export querry)

    Hi Guys I heared there is method to export error, warnings and info in microsoft excel sheet , if any one know then please share with me. Regards Shobhit
  9. S

    books on SOC AMBA architecture

    I think you are not right . I cant diagest it , "Combination of three is Called AMBA AHB" I think combination of three is called AMBA 2.0 and if the Newer Version AXI Comes in a picture with above then it will called AMBA 3.0.
  10. S

    Questions about sensitivity list in Verilog and what type of language is Verilog

    verilog questions Yes Tan u are right Inside process all the statements are sequential while others are concurrent. In Verilog we have blocking = and non blocking <= assigments .
  11. S

    VHDL Answers to Frequently Asked Questions

    I already have that book !!! I am asking about VHDL-FAQ !!!
  12. S

    Latches and flip flops

    One more this is that , Latch is level triggered device while flipflop is edge triggered , so if u use latched instead of flipflop then u will get lot of timing Voilations
  13. S

    Software used for simulation of basic VHDL

    Re: about VHDL... Basically VCS MX is Costlyiest tool in the Industry Because it supports a lot of languages VHDL,Verilog,SystemVerilog,SystemC,DirectC,Perl,TCL etc. so I think VCS is good for ure need. which supports only VHDL and Verilog few more. its a synopsys tool there is no demo...
  14. S

    [SOLVED] What is the gate level and RTL level?

    what is gate level?? RTL Level : Where some real code is written Mixed with Some Logic . GATE Level : Its after Synthesis. and only Instances are there but it also reuire a target library to simulate.
  15. S

    CRC Related Information

    Hi Guys I found following code on web for CRC-5 its simple XORing but I m confused how to calculate (which bit or crc_in is XORed by which Bit of din) its for ploynominal = X^5+X^2+1 if I want to calculte for CRC-32 then how can I decide which bit is XOR ed. Please clear my douts. please...
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