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In the fastscan capture procedure, can I use the condition statement for a programmable register/test point multiple times in different cycles with different values? For eg,
procedure capture CYC_CLOCK =
timeplate tp_capture;
cycle =
force_pi;
condition tp0 0...
In my design while inserting scan and doing testing, I have multiple chains, say Y chains each having X flops. Then in another mode of scan testing, I connect these Y chains together to form a single chain with X*Y flops. Is there any advantage of doing that?
with reference to the thread https://www.edaboard.com/threads/119311/ and the response posted by vlsi_eda_guy, can you please explain how SDD is tested sand how the patterns are generated? I couldn't understand why the patterns will pass and will that defect not be detected during functional...
I am new to verilog and have a doubt concerning the race conditions in the following code which is taken from FPGA Prototyping by Veriloog Examples by Pong P. Chu. The code is:
always @(posedge clk)
a = b;
always @(posedge clk)
b = a;
This will infer races depending on which always...
In the question below, the ASM chart shows that value of q_next is compared to 0 to proceed to next state but before q_next is compared, the value of q is already updated with q_next, so if we compare the value of q with 0, will the results be same in terms of timing and other parameters? Also...
I was going through a verilog code for time multiplexing with LED patterns. I am attaching the screenshot of the problem. I could not understand why they took the 18 bit counter because that would divide the frequency by 2^18 and not 2^16.
Hi,
I am studying the basics of dft techniques and is able to understand the basic definitions of controllability and observability in context of testing. What I am not being able to understand is how does adding scan design improves the testability, that is controllability and observability...
Can you please explain key shifting? Yes, I am testing the hardware implementation for my university project and not synthesizing it on FPGA but for timing analysis, I need to reduce the pin count to around 500.
I am working on the hardware implementation of RC4 cipher and has written the code for it using ASM design methodology and the key and plain text are given by the user through two input ports of integers. After running Analysis and Synthesis, the device uses around 800 pins and Altera Quartus II...
i am writing a vhdl code for a circuit which contains signed adders, not or operations and the inputs fed to these adders are of different bit sizes. will there be any advantage in synthesizing if I declare these adders as components and then instantiate in my code or direct instantiation would...
ok, then can you design it? what i did was i made the output logic of a mux as the output and put a clk and in clear signal, i put the complement of the clock so that when it goes low, the previous state is removed but it is still edge triggered
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