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Hello,
I am designing 4 bit carry sip adder using reversible logic using pass transistors in tanner s-edit v.15 0.25um technology at 2.5V. My results are correct for pass transistor realization of the individual reversible gates for all the input combinations but when I am going for 1 bit full...
Hello,
I am performing simulation of a complex cmos circuit in Pyxis,Mentor Graphics tool 130 nm technology and I want to know what is the acceptable output voltage level for low and high logic states in 130 nm technology?
Please help.
Thanks in Advance.
My design is
https://obrazki.elektroda.pl/3664205200_1493188981_thumb.jpg
Sir,this SG gate is not Sayem gate,it is Saini Garg reversible gate.And I have designed this gate by taking help from the below design.
https://obrazki.elektroda.pl/1076965500_1493189910.png
Thank You.
Hii..I am doing project on designing t flip flop using reversible gates(SG gate and Feynman gate)..My code is structural code with no reset input,only T and clock are inputs and Q is the output.The output toggles when clock and T is 1 but does not hold the state upto next T=clk=1.What could be...
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