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Thanks for reply. I considered the FIFO scenario. Decide a depth based on Data bursts. But thinking how to handle overflow during concatenation, any overflow should be concatenated with next incoming data with loosing. Important to note that any one of the data ( 8/16/32) arrives at each clock...
Any specific Arbiter in mind? Data arrives at every clock cycle, it can be 8-bit, 16-bit or 32-bit. But arrives one at a time, every clock cycle. If its a burst I might consider a depth for the buffer/FIFO/memory
Thanks for response. The final output receiver only cares if the data is 32-bit. Any other data needs to be concatenated to 32-bits and then sent to output receiver. Overflow after concatenation has to come in the next clock cycle, concatenated with next incoming data. The valid signals tells if...
Hi,
I have 32-bit data, 16-bit data, 8-data accompanied by their respective data valid signal. At each clock, any one of the data may arrive into 32-bit memory/buffer. If its 32-bit, I could send across the output. If its any other data, I need wait until the 32-bit is filled after...
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