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As a strict upper limit, it must be the number of paths in the design, right? For a practical limit, it must be tool dependent. I imagine for a modern tool, it's pretty large, but I'm afraid I can't answer better than that. Have you hit this limit? If so, what was it and for which tool?
best...
No and no.
Either:
1) you haven't read my responses;
2) you haven't understood them and aren't aware of it;
3) you're doing this on purpose.
Are you trolling me?
Hi Kuxx,
the first thing I think you need to do is specify input and output delays for your inputs and outputs. You should be able to find out what these are from the blocks that interface to yours that have already been implemented. Any blocks that haven't been implemented, you should be able...
Hi Kuxx,
I think the N/A entries come from the fact that either you have no reg2out paths, in2out paths or clock gates, or they're not constrained. Can you post some more details of your design? A list of inputs/outputs and the SDC file you're using? What happens if you simulate having...
An oscillating output is one possible manifestation of metastability; I didn't mean it as a definition. Outher behaviours might include, but not be limited to:
\[\to\] oscillations that do not reach valid logic '1' and '0' levels that may continue or stop spontaneously;
\[\to\] oscillations...
No. The input and output delays refer to the delays external (i.e. in A and C) to the block that you're implementing (i.e. B in this example). I've drawn these on your circuit diagram:
I've clearly marked these as input delay and output delay.
In that respect, combined with the clock period...
I've never done what you're asking, but am interested in hearing about your reasons for doing this, and if possible what your experience with this is. I have several thoughts I'll share anyway:
\[\to\] I've only ever used set_clock_uncertainty to add margin to the clock tree pre-CTS. I'm not...
I don't know what you mean by this. Your implementation tool will ensure the setup and hold time between the two registers is correctly implemented. The issue that was raised by ads_ee (that I agree with) is that you reduce the setup time available for the registers receiving the synchronous...
Are you sure this was the question you were asked? The set_input_delay and set_output_delay commands are needed to model the timing of your design in the context of the larger system. The specification of the clock is ok.
The input delay specification for block B should come from the clock to...
ads_ee is correct - the second register should be clocked on the same edge as the first. Your reset tree may turn out to have a high fanout and in this case the full clock period will help with the implementation. I don't mean to be a pedant but I find your schematic a little unclear: bear in...
You can do this sort of thing quite easily with a small tcl script: e.g.
set instances [ dbget top.insts ]
foreach inst $instances {
set box [ dbget $inst.box ]
set coords [ string trim $box "{}" ]
set x0 [ lindex $coords 0 ]
set y0 [ lindex $coords 1 ]
set x1 [...
The "right" way to resynchronise an asynchnronous signal into a new clock domain depends on the situation - there's no magic code example that is guaranteed to solve your specific problem. If you describe the specifics of the situation and make a reasonable attempt at providing a solution, then...
Hi Kuxx,
encounter won't try to fix hold violations if it doesn't think that any exist. Are you simulating and implementing against the same technology library? I.e. is the setup and hold window for the flop that encounter sees the same as the timing check in the simulation library?
Best...
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