Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
fractional pll sigma delta
hi
we must use a Delta-sigama Modulator to implenment a Fractional PLL. so i don't think there are differnces between normal Fractional ones you called and Delta-sigma ones. In fact ,they are the same. if you use a high order modulator, the period of the output...
i don't know which signal will be used as the input clock of the delta-sigma modulator in Fractiona PLL. the ref. clock or the clock divided by N-divider?
which is better, and why?
any suggestion is ok
pll design is hard.
first you should know the basic concepts such as setting time, random jitter and so on. you can read books or papes to get this.
then you can use matlab, veriloga or orther high level simulation tools to do some system simulation which i think is the most important for the...
two things you should make sure before you decide the Pulse width of PFD
(1) avoiding deadzone
(2) spur level as pulse width will affect the leve of spur
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
