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There are two types of timing analysis: Static Timing analysis and Dynamic Timing Analysis. Since STA will validate all timing paths in the designs under worst case conditions, at the same time it can't check the logical functionality of the design..so in this case dynamic timing analysis comes...
Hi,
If X is propagating in the scan output channel, how to know which scan chain is propagating X since there are more than one scan chains being compacted in the same scan channel.
Regards,
Shankhy
Thanks for the reply maulin...Just wanted to understand that I studied somewhere that due to power variance also chip sometimes fail on the tester so it can rectified sometimes in atpg by generating low power patterns also..I think it comes under power aware atpg...Is the funda correct?
Thanks for the reply...but can you tell me normally under which conditions the patterns can fail in the tester? I have also studied somewhere that generating low power patterns can sometime help in fixing this kind of issue? Is that correct?..
Hi all,
I wanted to know issues regarding post silicon debug like what happens when ATPG patterns fails in tester? What will be the approach to debug them?
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