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Hello all,
I needed to understand if anyone has worked with ITC'99 benchmarks and if they've found any particular benchmark which post synthesis would have clock buffers on the clock tree?
Any pointers will be greatly appreciated.
Thanks!
Hi,
I am trying to simulate some circuits using Synopsys 90nm model files but I want technology files with smaller feature size.
I was wondering if someone could direct me to such spice models.
Please help.
https://obrazki.elektroda.pl/4366424500_1361240377.png
I want to know the current source definition in HSPICE in this image.
The paper mentions it used current ramp with a slope of 3000A/us was used to generate at most 10% supply drop.
3000A/us - Can anyone describe how to write this current...
Re: HSPICE Code of 8 bit LFSR
Hello ,
I am facing few problems yet with the simulation of this 8 bit LFSR (figure attached )and I am guessing its because of the way the 8 bit LFSR is getting instantiated.
Can anyone tell me what could be the reason behind the clock pulse getting generated...
Re: HSPICE Code of 8 bit LFSR
Keith ,
The job concluded with just this change itself -Vgnd GND 0 0.
Cant believe I made such a stupid mistake :wink:
Thank you very much :)
Hello all,
I want to simulate 8bit LFSR in HSPICE . The following is the code that I have written :
.include technology_file.sp
**************************************************************************
**** Parameters
**************************************************************************...
Hello all,
I wanted HSPICE netlists of any sequential benchmark circuits if you have. I will appreciate if you can guide me to the page where I can download and use them.
Thanking in anticipation
Hello friends,
I have RTL design with me which I have synthesized using DC and created gate-level netlist. I have to simulate this gate-level netlist with the cell library and testbench in Modelsim. The issue is I only have a.lib file with me and not a .vhd file of library with me .
I did...
You are supposed to read in the netlist in the DFT Compiler tool and all these commands to be executed in DFT Compiler. The output of the DC tool i.e. synthezized netlist acts as input to this DFT Compiler tool .
I dont know if Synopsys DC has in-built TEST compiler or not, but yes if you want to do full-scan_boundasy scan you can use the tool DFT Compiler from Synopsys. Your first step should be to read in the systhesized netlist which you got rom DC as input to the DFT Compiler tool.
Few essential...
Can any1 help me to point out the error with this to identify a bufferchain? Thanks in advance :)
proc buffer_chain {} {
set buffer_inv_cells [get_object_name [get_cells -hier -filter "ref_name =~ BUF*" ] ]
foreach cell $buffer_inv_cells {
set bf_temp [list $cell ];
set i 0...
Hi Vijay , Thanks :)
Your script does count the buffers but I guess its not having the logic of checking the presence of consecutive buffers. can you elaborate a little more how you were suggesting using "if statement "?
And thanks for the summary command too :)
I want to do something like this on parallel grounds. I need DC-TCL script for checking a chain of buffers/inverters in a netlist. can some1 please point to some script which can help me over it.
Thanks !
Usually we aim for >99% Fault Coverage for stuck-at-faults.
What makes it so difficult for Delay tests that we surrender once we have close to 85% fault covergae in them ?
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