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hi,
can i use if else inside generate statement?
generate
for (i = 0; i < my_size; i = i + 1)
begin : size
u_mux(.in(index[i]),
.sel(idx_int[i]),
.out(side[4*i +: 4]));
if (i == 'd0)
assign my_data[64*i +: 64] =...
Hi Vijay82, I don't have knowledge about DFT. The only thing that I understood after reading some articles was that we use lockup latches for dft when we are stitching flops from domains where no logical paths exist. That is when this question popped in my mind.
thanks ads-ee.
I was looking for depth of fifo in asycn clock cases when read freq> write freq.
Because the read is happening more often and we want fifo only for synchronization, i think 2 deep fifo should do, " irrespective of the read/write freq value". This is my assumption. I am not sure...
hi,
I have a case where the scan stitching needs to be done between 2 async clock domains. I know that we need negative latches as lockup latches when we stitch two posedge triggered flops from asynch clock domains. My question is, for this particular case in the figure, is the hold time meeting...
how would we determine the depth of fifo in that case? Taking the same example,
"my read freq is 200Mhz and write freq is 100Mhz. and bytes are written and read at 1 byte per cycle." A burst of say 8 bytes is the max load that can come on the write side.
Can i just work with a two deep fifo?
As i said, my read freq is 200Mhz and write freq is 100Mhz. and bytes are written and read at 1 byte per cycle. Cant we work with just a synchronized enable signal which will enable read at every second cycle? why do i really need a fifo?
Hi sharath666,
My question is, of the write clock frequency is 100mhz and read clock freq is 200Mhz. The data is written and read at 1 byte per cycle, do we still need a fifo in case 1) when clocks ate synchronous and 2) when clocks are async
hi ads-ee,
No they are not from my homework :smile:
I am studying and trying to learn digital design concepts at my own.
I am referring to many books, blogs and sites to grab this basic understanding.
Apart from certain rtl coding doubts, which i could resolve at my own, I was facing issues in...
Hi All,
I am facing difficulty in understanding certain concepts.
Could you please clarify my following doubts:
1) Is there any example of having an intentional combo loop in design? Can combo loops be useful? How does synthesis tool and gate level simulation act on combo loop. How do we meet...
hi,
I have a module which is such that
module code3b (o, a, nrst, en);
output o;
input a, nrst, en;
reg o;
always @(a or nrst or en)
o = latch(a, nrst, en);
function latch;
input a, nrst, en;
if (!nrst) latch = 1'b0;
else if (en) latch = a;
endfunction
endmodule
Will this infer a latch or a...
project on opamp as integrator
The circuit should work. The W/L variation can also be done in simple multiples of 50/2 or so.
For a 1st order design, you can take the parameters as:
1)SR = 10 V/usec
2)Av = 5000 V/V
3)GB = 5 MHz
4)CL = 10 pF
5)Pdiss < 0.3 mWatt
6)ICMR+ = 1.5 Volt
7)ICMR- = 0.2 Volt
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