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Nice one.....I have one doubt regarding AHB.
If in the same cycle htrans is BUSY and hresp is error with ready zero then what should be the htrans in the next cycle i.e. while error and hready is 1.
Reply people i got stuck there.
Hello to all......
If master asserts htrans as busy and in the same cycle slave gives hresp retry and hready low for the previous transfer as response then what should be the htrans in the secons cycle of retry.
Thanks Dave Rich.......
I have tried with this but it is unnecessary firing assertion even one of the condition is true at that point what i want is any of the condition should be checked for example if x=4 then i want to check count is 7 or not thats it....once x==4...
hello to all..
i want to write assertion for following condition.
bit [3:0] x;
bit [5:0] count;
whenever x is 4 then i want to check count =7, whenever x=6 i want to check count=9,whenever x=7 i want to check count=11. please help urgently
Thanks for ur help...
Actually in my case b is varing between 0,1,2,3 but now what i actually want is after b=0 b has to be 2 whatever may be the no of clock cycle but once b changes it has to be 2 only b=0 can be for 5 clock cycle but what i want when b changes again...
hello to all....
i want to write the assertion in systemverilog for following condition
currently b=0 now whenever it changes it should be 2. b=0 may be for n number of clock cycle but whenever it changes it should be 2 i want to write property for this.
thanking you all.
hello...
I am a beginner. i want to understand the concept of clocking block in interface and some concepts use to develop the systemverilog base test bench can any one suggest me good source for the same..?
Thanks dave_59
ya you are right.. but in Testbench.in they have shown the concept but i want the small code for the same to understand how it really works in systemverilog.
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