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TCLK is one of the ports of my memory. Each memory have port CLK - functional clock, and port TCLK - mbist clock. Port TCLKE is a selector between these two clocks.
My tessent flow looks like:
create "mbist_clock" port on the top level. Apply add_clocks command to " mbist_clock" port i.e...
Thanks.
Of course, I'v learned the "Tessent Core Description" format well. But the problem not in *.tcd description of memory.
When the tool have connection and driving ability for "EmbeddedTestLogic" ports TCLK and TCLKE, tool also wants a clock on a functional port CLK. But it's not matter...
Thanks for answer.
Tool doesn't, but memory compiler does.
Memories with dedicated test clock also have all other test logic inside. For such memories Tessent tool doesn't place collar and other test logic. So, this makes possible to reduce test logic in all.
Hi folks.
I have single port memory with a dedicated test clock port, i.e. in *.lvlib for clock port:
Port (CLK)
{
Direction: INPUT;
Function: Clock;
Plarity: ActiveHigh;
EmbeddedTestLogic {
TestInput: TCLK;
}...
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