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Recent content by sergeyr77

  1. S

    which tool do you use for behavioral modeling

    I use verilog-A( with Spectra), but calculations using matlab. ASCII file is from tran simulation. Industry
  2. S

    Does LDOs PSRR can simulate the stability of the regulator?

    Re: LDO's psrr To verify stability of LDO your must apply a small votage step at the input, then current step at the output (votage step via small capacitor) and voltage step above power supply. Criterion of stability- at most one ring of transients at the output
  3. S

    Help me design a 80dB opamp with 10uF capacitance load

    Re: A OPAMP design With such a big Cload you can use 2 stage amplifier without compensation
  4. S

    How to simulater Oscillator

    It means that gain of corresponding amplifier at working frequency is low. I usually make AC analyses of open loop to check Nyquist criterion- it saves a plenty of time.
  5. S

    about sfdr of 14bits dac

    You can find a good explanation of simulation techniques at CMOS Mixed-Signal Circuit Design by R. J. Baker
  6. S

    where to find crystal oscillator equivalent parameters?

    Parameters of crystal depends on manufacturer, frequency range, quality. You can get equivalent parameters from Data Sheets ( Fox, etc). Of course crystal parameters don't depend upon circuit connection - Pierce, etc
  7. S

    How to design a sigma-delta ADC and Decimator?

    The simplest decimator it is a counter - first order digital filer+ decimator. For this case modulator must be also first order. Design is very simple - 1 OpAmp, 3 capacitors, 1 comparator-latch.
  8. S

    How to simlulation the stability of a LDO?

    1. AC check of phase margin, no matter closed loop simulation or open: plots Vfb/(Vin-Vfb) both for phase and magnitude. Criterion PM > 70 2. Trans. Steps at the input (line regulation) and disterbance at the output (load regulation). No overshoots are allowed
  9. S

    analog parts in digital design process

    There are no analog libraries such as standart cells, I/O, memories, etc. If you cannot design analog block (ADC, DAC, PLL, etc) yourself, you can obtain it from the third party. Distribution contains HDL description (Verilog and VHDL is commonly accepted) and optionally netlist, layout...
  10. S

    Power-down and startup circuit for bandgap?

    Use nmos transistor conrolled by power_down signal connecting all gates of nmos transistors and gnd. It prevents current sinking. At the same wave put pmos transistor (switch) controlled by (power_down)' signal connecting all gates of pmos transistors and vdd. It prevents sourcing from vdd. When...
  11. S

    what's CDF of cadence?what's usage?tks!

    cadence cdf user guide CDF is a set of analog properties that has any cell in dfII database, including primitive, subcircuit, schematics, etc. You can define here netlisting procedure, parameter parsing. It is very powerfull tool.
  12. S

    Why contact and via have exact size ?

    Re: contact and via size This is due to yield problems. Actually it is minimum opening size. PS. If you need more contact/via area ( for reducing voltage drop on it, for elecromigration issues, etc) icrease number of contacts.
  13. S

    how do I calculate the current in a cascode current mirror

    Re: how do I calculate the current in a cascode current mirr This circuit will work at any voltage at any technology. Vth is parameter that marks two regions- subthreshold (weak inversion) and strong inversion.
  14. S

    how do I calculate the current in a cascode current mirror

    Re: how do I calculate the current in a cascode current mirr Usually current is calculated with very well known formula of Id.... Spice programs calculate it very fast.

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