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I had one case that I had to use not 4-terminal (Drain, Gate, Source, and Body) but 6-terminal transistors (D, G, S, B, and DNW-deep nwell, PSUB- psubstrate). These diodes should be connected between PSUB and DNW - dnwpsub one; and between pwell (body of nmos) and DNW - pwdnw. Probably you have...
There is hard to see details in layout, so I can only guess.
1. Check if you have connections from transistors to substrates (bodies).
2. If yes, the technology you are using can be triple well. In this case it is possible do add these diodes (dnwpsub and pndnw) to inverter schematic.
If you make layout as small as possible (of course meeting DRC rules) the connection lines are shorter. So it seems that paracitic capacitors are decreased. But at the other hand the separatrion between metal paths is also smaller so the parasitic capacitance can even increase. So, one should...
Your question is general and it is not easy to answer it shortly. I assume that you mean the diffeerences between schematic and post-layout simulations.
Schematic only simulations takes into account only devices that are presented in schematic. But real (fabricated) device will have not only...
After depositing or grow of dielectrc layer (in fact any layer), this layer is polished. So we can assume that the height (what I called depth) from the top surface of dielectric to the polisilicon layer is smaller than to the diffusion layer. As you noticed "Gate and Diffusion are not on the...
The contact is the hole etched in the dielectric. So in both cases (poly and diffusion contacts) the process looks the same. In fact the depth of diffusion contact is greater.
But you cannot say "Metal to Poly is through CONTACT. Whereas Metal to Diffusion is through (CONTACT + dielectric space...
The same contact size is defined by dielectric etching process. This process requires specific size in X and Y directions in order to ensure proper quality of that "hole".
The depth of this "hole" rather doesn't matter because etching process has to remove dielectric only. It is chemical or...
Re: measurement of mosfet capacitance (C-V plot) ?
You can add (small) resistor to make low-pass filter. After this use dc voltage to set operating point of transitor (this will be voltage in your plot) and ac source. Make ac analysis and find 3dB frequency. Calculate C (you know R and f3db)...
Up to now VerilogA is used rather to modeling and simulation of analog circuits. It is hard to synthetize schematic/layout from such code. I have read that there were some tries to do such tools.
Simplifying, the contact can be treated as a hole in the thick dielectric (e.g. di-oxide). During depisiting metal1 layer, the atoms of this metal goes also into such holes and make contact from gate or drain/source area to this metal. Thus contact is the same metal. So it is not difference if...
The basic ones are:
1. DRC- design rule check - it checks geometrical rules of drawn layers
2. ERC - electrical rule check - it checks electrical issues, e.g. shorts, unconnected nets (it is usually done together with LVS)
3. LVS - layout versus schematic - compares if layout corresponds to...
The real voltage source can be represented as serial connection of ideal vdc and imperance Z (this is zero for ideal case). Current source is usually represented as parallel connection of ideal current source and admittance. Admittance Y = 1/Z. In ideal case Y=0, which gives Z = infinite. Thus...
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