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Recent content by sengyee88

  1. S

    Photodiode- process requirement

    photo diode process Hi, If I would like to develop photodiode onto silicon wafer, what kind of info i need from foundry? I am looking for standard 0.35um CMOS process, is it all CMOS processes can have integrated photodiode?
  2. S

    About CMOS opamp's offset

    Make ur open loop gain high will suppress input offset.
  3. S

    the difference between avg and rms?

    RMS= 1/sqrt(2) is only valid for pure sinusoidal. RMS of a square wave is actually equals to the mid point of the square pulse.
  4. S

    Please expain to me why DLL has no jitter accumulation...

    jitter accumulation vco Because DLL has clock input, it is just a delay element for the input clock. It will resynchronized to input and jitter accumulation will be reset. PLL do not has input clock, it generate its own clock from VCO. Hence, jitter will be accumulated.
  5. S

    HSPICE/SPECTRE/ELDO question

    spectre eldo For spectre, you can run the 1st simulation (0 ~ 15us) and save the final transient results into a file. If you look at the transient simulation syntax: "tran tran stop=15u errpreset=conservative ...", you can add "writefinal="<filename>.fc"" to the syntax. It will save the final...
  6. S

    about mos bulk connect

    If additional pad is allowed, I would prefer all mos' bulk connected together, then connected to off chip voltage through pad. If no additional pad, mos' bulk on sensitive blocks should not locally connected to supply. They can eventually joined at top level, as top level normally has supply...
  7. S

    Question about NMOS capacitor

    Re: About mos capacitor If there is only a capacitor, I think both make no difference. If you want to match 2 cap with the same dimension, square structure will be better. Considering sidewall cap M2 has bigger cap.
  8. S

    Question about amazing comparator design technique

    I think the feedback cap provide positive feedback that improve (shorten) the transition time.
  9. S

    How to understand this Bias Circuit?

    I think the current through 3 branches are not equal. Assuming I1=first branch (current through Q2) I2=2nd branch (current through Q3) I3=3rd branch (current through Q7) You can derive that: I2*R + Vbe5 +I1R + Vbe2 = Vbe4 + Vbe3 Hence, Eq 14 = I1 + I2 Vbe4 + Vbe3 = Vbe7 +I3R6 Hence. Eq15 = I3...
  10. S

    Differential pair questions

    As mentioned, remove the ideal current source. Replace by a current mirror. You will see that if your inputs=0, no current will flow through.
  11. S

    How can this equation be equal?

    I think it is: Pn=4x10^-12W =4x10^-9 mW =10log(4x10^-9) dBm =-84dBm
  12. S

    amplifier input resistance

    Think about a scenario that the previous stage output impedance is 10KOhm, and your amplifier that connected to it has input impedance of 10Ohm. Do you think you will get any signal out from your amplifier? Having low input impedance for voltage amplifier effectively means that you are...
  13. S

    back to back diode in transistor

    Message is unavailable.
  14. S

    what's the trend of vth when width or length goes smaller?

    Re: what's the trend of vth when width or length goes smalle Is the bulk of the transistor connected to source or supply line? If Vsb≠0, Vth will change with transistor size.
  15. S

    What is the usage of the PMOS in this simple amplifier?

    I guess it will not turn off. Having large L and small W can limit the current flowing through it,
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