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Recent content by seeker_123

  1. S

    Gearbox design to compensate PPM

    I am looking for 32 to 40 bit gearbox design at receiver. Clock frequency at write and read side is same but not from same source. One is recovered and other is generated at receiver. Concern is PPM which is +/- 200. Write side 32 bit input is continuous while read side 40 bit output has one...
  2. S

    Test vectors for ripemd160 hashing algorithm

    Hello ads see Those codes are working fine with me now. Needed few changes before running on my machine like declaration of dword has to be changed from unsigned long to unsigned int. and they are giving exact answers as expected. I think now I can modify these codes for each round outputs...
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    Test vectors for ripemd160 hashing algorithm

    I am taking care of end of line also precisely. Yes there is bit change from both sources. I tried with codes from dr Dobbs website. But results are same. is there anything special to take care about while running these codes? (like 32 bit or 64 bit os version) Because its hard to believe that...
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    Test vectors for ripemd160 hashing algorithm

    Ok. I will do that sir. thank you - - - Updated - - - yes I am taking care of that. But currently I am trying to get round wise output for which I am using c implementation of ripemd 160 which I have mentioned earlier. I am directly giving message through file which has message as it is in...
  5. S

    Test vectors for ripemd160 hashing algorithm

    thanks ads-ee I tried using Dr.Dobb's c implementation which is given at https://homes.esat.kuleuven.be/~bosselae/ripemd160.html But I am not sure that implementation is correct. Because i tried giving some inputs for c code. But final hash results are not matching with expected standard...
  6. S

    Test vectors for ripemd160 hashing algorithm

    Hi, I am trying to test Ripemd160 hashing algorithm. I have checked my results with online test vectors and ripemd hash generators. But my outputs are not matching :sad: . So I am trying to debug it:fight: So if I can have test vectors which gives output for each round then that will be...
  7. S

    suggestion for best synthesis tool for asic design

    Hi I want to know best synthesis tool for asic design. From web i have listed some like 1. Design Compiler by Synopsys 2. Encounter RTL Compiler by Cadence Design Systems 3. HDL Designer by Mentor Graphics 4. TalusDesign by Magma Design Automation I know it might be difficult to say...
  8. S

    srt division for floating poin coprocessor

    Hi all I am looking for srt division algorithm (look up table based) for floating point co-processor. I have searched for document over internet. But I am not totally clear about it. I have gone through "division algorithm and implementation" by stuart F oberman and M Flynn. But truly...
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    preferred design for floating point comparision

    thanks std_match (I am already having subtraction unit in design) So is it the case that if one is having subtraction unit then no need to go for separate unit for compare.? Because subtraction unit is time consuming than compare unit (more delay or latency). Then I think we have to choose...
  10. S

    preferred design for floating point comparision

    thanks everyone, Ok means normal comparator is better. Then why arm using subtraction operation for comparison http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Cihiddid.html is there any valid reason. (though this is for integer comparison)
  11. S

    preferred design for floating point comparision

    Hii I want to compare two floating point IEEE754 numbers For this which is efficient hardware design one with normal comparator like ( just comparing sign, exponent, mantissa of both operands with < == > sign ) or with subtraction method ( operand1 - operand2 depends on result one can...
  12. S

    How simulation tool maps rtl code

    Thanks Dave Its really helpful simulator internally maps rtl code to some different way. Like I mention one example in my first post, for swapping two registers actually "temp" is nowhere but simulator tool may introduce some logic like this to mimic actual hardware(not visible to user)...
  13. S

    How simulation tool maps rtl code

    Thanks miralipoor for this example I know. I want to know some more example. so if you can provide then it will be helpful Thanks
  14. S

    How simulation tool maps rtl code

    Hi everyone I am looking for how simulation tool(modelsim) and synthesis tool maps RTL code. In this I am not getting much information on how modelsim maps rtl code. How simulation model works ...? can anybody help me in this ..? Here is example like always @(posedge clk) begin k2 <= k1...
  15. S

    diff between Keep Hierarchy and netlist Hierarchy

    Hi what is diff between Keep Hierarchy and netlist Hierarchy in ISE synthesis constraint Because If we are giving rebuild as heirachical constraint then keep constraint is ignored then why to give keep constraint. and if we are giving yes to keep constraint and as optimized in hierarchical...
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