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The ports are on the right layer. From where can I define the absolute dimension for mesh size (um). I could not find this option. Can we use this option to set dimensions for each layer separately ? But it will increase the simulation time a lot.
I simulated the same problem in ADS momentum to see the difference. See the attached pdf file. My frequency of interest is 110 GHz to 250 GHz. And the minimum width of the via is 0.19 um. For me the ads mesh looks less denser for such problem. Could you please comment on the momentum em setup...
Sonnet standard and internal co-calibrated ports giving different results
Hi,
I am simulating the interconnection between four transistors as explained in the attached pdf file. The transistor is in the form of BEC (Base Emitter Collector). In the file you will find that I made a connection...
I tried it by making the distance three times the substrate thickness as suggested in the manual but it gave almost same results. However, in this case it took more time. How about the local ground plane ? if we want to define a local ground plane then we just have to connect that metal layer to...
It means that if there are no box resonances then we can accept the results depending on the mesh size and port setting. I simulated the same structure in ads momentum with 45 cells/wavelength but the results were different for S11 as you can see in the attached file from 160 GHz to 220 GHz.
Another thing which I almost forgot, is this definition of local ground correct ? Is it compulsory to make the sonnet box far from the circuit ? If I want to make it far from the circuit then, I have to increase the length of the I/O lines and increase the reference planes which will require...
Thanks I will read that Topic. Are there any online materials about EM simulation of ICs at very high frequency in ADS momentum ? I am designing analog integrated circuits at mm waves so far I am using Sonnet and it is taking too much time and memory.
Thank you so much. I will use ADS then. Are there any publication at high frequency about IC design done with ADS. If you have know could you please share it with me.
Yes, I compared it with ADS momentum and both gave same results. The sonnet took a lot of time in calculating DC and RF frequencies. I am designing the matching network in a way to include the biasing circuit inside matching network that is why I am simulating DC.
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I am not...
This is what I did. Thanks for your reply. I figure it out. the problem comes if you change the default frequency to 1 Hz or any other small frequency for DC.
Hi everyone,
I am simulating a simple combiner in Sonnet but I am getting strange results (specially at DC). Let me describe the combiner shown in the Figure 1. The combiner has a width (metal 5) of 18.5 um that will be connected to bases of transistor through vias because the contacts for...
I am sorry for so late reply. I was checking the threads again and found your simulation in Cadence. I did the simulation for ft/fmax in ADS. However, I got ft/fmax greater than the one specified in the IHP design kit. There is about 70-80 GHz difference. I think at frequency the model becomes...
I tried to design the PA in class B operation region. It seems at high frequency the transistor has almost no gain in Class B region. That is why people are biasing the transistor near peak ft.
I asked the author of the paper and he mentioned that if you are biasing the transistor at high biasing current then you are automatically in class A operation region otherwise you can be in class AB, B or C.
In 0.13um SiGe process the IHP has not specified the maximum current of transistor...
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