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Recent content by satishbabub

  1. S

    error in verilog code for alu test bench

    hello guys .. i was trying to write verilog code for alu testbench ...my code is posted below ..its far from complete but i was trying to test one of the functionality(adder) by providing the select signal and inputs A,B are my inputs and F is my output .. the problem i was facing is the value...
  2. S

    clock multiplier in verilog with model sim

    i dont want a synthesizable code ..i just want to run a simple simulation whose output should have a period twice hat of clk ...
  3. S

    clock multiplier in verilog with model sim

    hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput...
  4. S

    error in verilog output code for counter testbench

    thanks ,found the error...
  5. S

    error in verilog output code for counter testbench

    hello guys can u help me with this ? i have written a simple verilog program for counter and its testbench as well.but the counter output either stays at one or zero rather counting . what kind of signal do u expect me to give at waveforms for reset and enable ?...here are the codes module...
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