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With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
plz anybody answe this question
one more question
for 2 year experience wat questions(topics) i can expect in interview apart from my project....
hello guys,
i came to know that physical design is not supporting for low tech like 20nm,18,15nm
if so wat abt this stream...due to over leakage and many issues....
is this true
provide ur opinions please
hello ,
can any body please explain
1 what is intrapolation and extrapolation points?
2.how tool will calculate these points?
add if any materials do u have .....thanks:grin:
hello,
when i m giving max delay and min delay then what is the use of giving skew..... (mainly in cts spec)
may be small question....i scratched my head.......
hello,
1.consider both congestion & large irdrop has occured...for reducing that i have to place decap cells...here already i have congestion...
so what may be the solution for this
ps: AMD interview question.... plz give right answers
hello,
1. why do we increase drive strength?
a. improve the slew rate(ii.e reduce slope of the signal)
for ur question i think it is depend upon ur load capacitance of those 8 nor gates..
this is the reason for which we are going for max transition vioaltion...
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