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hello
iam working on h264 video compression, and i have done coding in vhdl, now i need to implement in FPGA kit, but i don know how to give .yuv file as input to fpga kit. iam new to fpga so can u plz help me out.
thankyou.
range is empty (null range)
hi all..
iam using xilinx 10.1 as a simulator for my project. iam implimenting h264 video compression transformation and quantization, while simulating the code iam getting the following warnings and errors
WARNING:HDLCompiler:746 -...
sample_int.yuv
hello
I am writing a vhdl program for h264 video compression transformation and quantization and i run it in modelsim but it gives me the following error
** Error: (vsim-7) Failed to open VHDL file "sample_int.yuv" in rb mode.
# No such file or directory. (errno = ENOENT)...
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