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Recent content by sasi_badveli

  1. S

    printing pcb layout on altium

    hi In altium designer, u can see layer tabs in the pcb editor. when u right click on the on one tab(suppose on top layer),u can find an option named flipped/flip. I think this is what u were asking for and hope it helps u.
  2. S

    [SOLVED] DDR2 SDRAM controller(generated using MIG) for spartan 3A FPGA

    Thank you so much for making it clear.
  3. S

    [SOLVED] DDR2 SDRAM controller(generated using MIG) for spartan 3A FPGA

    @cristianp:Thanks for the reply. Can you please explain that in the memory module which i mentioned, in data sheet "-37E" refers to a latency of -4. Also in the micron website, h**p://www.micron.com/parts/dram/ddr2-sdram/mt47h32m8bp-37e-it?source=ps&q=MT47H32M8BP-37E%20IT, Can a memory...
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    [SOLVED] DDR2 SDRAM controller(generated using MIG) for spartan 3A FPGA

    @cristianp: Thank you for the reply. Can u explain for the following example? If the fpga used is (XC3S200A-4FTG256)spartan 3A and DDR2 SDRAM memory module is MT47H32M8BP-37E? I tried to generate a DDR2 memory controller using MIG tool.But it turns out that the MIG tool does not support...
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    [SOLVED] DDR2 SDRAM controller(generated using MIG) for spartan 3A FPGA

    Hello all, I have few questions regarding CAS Latency. For example,if the DDR2 SDRAM consists of a CAS Latency of 4,and if the DDR2 SDRAM memory controller generated using MIG has a latency of 3? Does the design work together? Any help would be appreciated. Thanks.
  6. S

    need information regarding file handling in verilog...

    Hello yura717, thanks for your reply.but can u please answer whether these file handling functions are written or used only in test benches?
  7. S

    need information regarding file handling in verilog...

    Hello all, where can i find more information on saving data stream into a file in verilog?I am new to the file handling functions in verilog.Are file handling functions used only in test benches?Any help would be appreciated.
  8. S

    generate clock of frequency 1MHz from an external clock of 100kHz using spartan 3A?

    Thank you all for your replies.
  9. S

    generate clock of frequency 1MHz from an external clock of 100kHz using spartan 3A?

    I just wanted to know whether it is possible to generate high frequency signals from low frequency signal.I know that u can do that by using DCM.But the minimum frequency should be 5MHz.so i wanted to know is there any other way. Thank u for reply. So u conclude that there is no solution for it?
  10. S

    generate clock of frequency 1MHz from an external clock of 100kHz using spartan 3A?

    Hello, I would like to generate a clock of frequency 1.6MHz from an external clock of 100KHz using spartan 3A FPGA?i am using verilog HDL for programming.I am very new to FPGAs.I would appreciate help and suggestions. Thanks in advance.
  11. S

    package which consists of set of current mirrors

    Thank u all for posting
  12. S

    package which consists of set of current mirrors

    Package i meant here is an IC. ---------- Post added at 09:30 ---------- Previous post was at 09:27 ---------- I mean,I need an IC which takes one input as a current of 20uA and gives same current as 20 outputs.I need that kind of package for testing.
  13. S

    package which consists of set of current mirrors

    hello all, I need to use 20µA of current to bias each transistor,and there are total of 20. Is there any package which consists of 20 current mirrors ? thanks in advance.
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