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Hi,
I had been looking for the same stuff about 6 months back but as far as I remember I didnt find anything useful either on IEEE or google search. I suggest that you could try using some switched capacitor techniques.
Hi,
Could you be a bit more specific on what kind of PA you are designing, i.e. in terms of class of operation, technology, and the specs you are targetting. I have personally design PA at 30 GHz and have a rteasonably good understanding of high speed designs.
well one thing I do know is that the dI/dV thing usually gives a wrong picture in the way it is done in Cadence. I remember once having used Cadence to get the value of slew rate for an amplifier and got some crazy values bcos of the way Cadence calculates differentials. So use it with caution...
Clock design
I dont have any particular specs. I need to learn it as I am going to be working on clock design in the near future and I do not have much idea of the area
while sedra gives an analysis at elementary level... gray and meyer does a more detailed analysis at different levels... I suggest gray and meyer wud b better of the two for ur needs...
My experience is that beyond 3 levels, the cascade doesnt work as the delay introduced by itself offsets the delay due to output cap. One method could be to progressively size the inverters in the cascade so as to reach the desired drive...
Re: reduce the noise
The effects of noise also depend on the kind of circuit one is making. For example, 1/f noise etc. are not signivficant when one is designing amplifiers in the Gigahertz range in modern technologies.
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