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I am unable to setup the initial steps for reading Verilog file in ICC2, Before I was using ICC and It was easy but ICC2 is so confusing.
I appreciate your any help regarding this.
I have designed analog circuit on cadence following SENT datasheet and it is working well as with the given data and is been received,
but now As SENT uses CRC and tick-generator So if I design these blocks using Verilog and generate layout but where am I suppose to put them
I didn't able to...
I am designing single stage CTLE equalizer the goal is 6.4Ghz Nyquist at 12.8Gbps, So in cadence simulation What frequency should be set. and how to see frequency in output waveforms?
When designing CTLE, of a particular frequency, say 6.4 GHz what is this implies where in tis implies where in the graph, Plz explain what makes it that it is a this frequency CTLE equalizer?
Please provide tips how to solve MOS problems for finding voltage gain and output Resistance. Like not by following small signal model but more intuitively and applying direct voltage and current formula on points.
Thankyou for your reply,
Actually that was my confusion that the several papers that I saw there were two frequencies mentioned. and I tried both with changing the RC value for impedance matching to get same output as input and found out that the frequency less than 125K it is working well
1...
What will be the suitable frequency range for SENT interface, for 0.03u technology in cadence?
Please explain what can prove that this is the good frequency for my receiver circuit?
In a paper two frequencies are mentioned one is 125KHz clock and other 625Mhz which should be used while...
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