Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by sarah1

  1. S

    Testing counter for testibility

    Hi,I am new here.Any body could answer the problem would be much appriciated.I dont have much time I need to do it before deadline I have got a 16 bit up- down counter with asynchronous preset and synchronous clear.how would you design it for tetebility.
  2. S

    why do we feed DFF with asserted low clock pulse?

    When clock gating why do we normlly feed DFF with asserted low clock pulse why not high?

Part and Inventory Search

Back
Top