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Recent content by santu7885

  1. S

    problem in netlisting..orcd16.3

    Hi every one, I am working with orcad16.3. I got some errors in making netlist file and its failed. please tell me a correct solution for this. These are the errors I got... #86 ERROR(SPCODD-86): Null pin name found for PIN_NUMBER on line 819. To avoid such problems, use Part Developer to edit...
  2. S

    copper area with gnd connection

    helo!... You just make an obstacle as corre pour and attach the ground net to it...thats it...
  3. S

    Applying constraints to track length in Orcad layout

    Hi satanam, why dont you go to spread sheetand change the properties and constraints for track width there...
  4. S

    Potentiometer Footprint issue on PCB Editor

    Yes marce, its working . thank you so much for help.
  5. S

    help me to get rid of this warning..in making gerber files..cadence16.3

    ... I didnt get you, what is its meaning (db doctor)??and how should we go db doctor?? .... I am using cadence16.3...
  6. S

    Potentiometer Footprint issue on PCB Editor

    you mean copper pour shape there instead of track??
  7. S

    Potentiometer Footprint issue on PCB Editor

    Hi, keith and FvM, please let me know....can I put track/line in foot print itself....?? When I am doing artwork, its diaplaying DRC there.... Please help me.....
  8. S

    Potentiometer Footprint issue on PCB Editor

    Hi sachin, I also faced problem same as like you.... I am working with cadence16.3.... I am also having doubt that can I put track/line in foot print itself??..... Please answer this and then we can go for solution..
  9. S

    please help me...in changes in silkscreen font in cadence 16.3 pcb editor

    thanks you so much pushpa... for that i have edited my footprints and updated them in my design... so again i edited text on silk screen to place them in proper positions in design... It became a big mess and killed so much time... but your idea is good and i will use that now onwards...
  10. S

    Is there any readily available foot prints for tqfp-80 in cadence16.3??

    Hi, I am working in cadence 16.3, I am preparing foot print for TQFP-80 microchip IC, I have the mechanical layout of the (land pattern) of the component... But I want to know, Is there any possiblity to get readily available footprints for them??
  11. S

    Orcad pcb editor help

    Instead of editing the existing footprint better you start making a new one, if have the pad and footprint mechanical details. If you know the pad details then you can prepare the footprint, with those mechanical dimensions i.e pad to pad gap and IC width.... If you dont have the pad...
  12. S

    HOW do you create a footprint for use in Allegro 16.3 in general and for TSSOP 28.

    All standars package footprints are avialable in installed directory only... If they are not enough , you need to prepare them... most of the pad stacks also available there...you can use them for your footprints...if they are not enogh for your design..you need to modify available pads...
  13. S

    PCB design and choosing number of layers

    thank you marce... I completed my layout and I am doing artwork for each layer.. Now I am facing problem with silkscreen bottom...top bottom and silkscreen top are completed... Please find the attached here... If possible give the solution.... components placed on bottom layer and it is SMD...
  14. S

    help me to get rid of this warning..in making gerber files..cadence16.3

    Hi senilicus, I have defined rectangular pad... top and soldermask top are defined as shown in fig attached... components is placed on bottom layer...
  15. S

    help me to get rid of this warning..in making gerber files..cadence16.3

    hi... please help me... I got this warning when doing artwork for silk screen bottom.... "WARNING: Null REGULAR-PAD specified for padstack SMD100_64_DIODE at (-2327.60 -2250.00)"... for all SMD components pads... I got this warning... thanks in advance.....

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