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Doubt in Logical Library
for a given cell, the logic library contains both delay of the cell as well the output transition for a given set of i/p transition and o/p load. cell_rise/cell_fall is the actual delay of the cell while rise_transition/fall_transitions are the o/p transition of the...
hold uncertainty
Hi,
I have seen that hold uncertainty is always less than setup uncertainty. Shall we discuss for the possible reasons behind it??
Thanks in advance....
magma primetime correlation
Hi,
Im reponsible for check correlation between timing reports generated by MAGMA and Ptime ( ran using sdf, sdc and netlist generated by MAGAM). But i found there is lot of difference in slack values.
Please advice me, what might be the reasons for this mismatch.
help me
Hey, its simple.
If your counter becomes ZERO as soon as your reset is enabled, then it is independent of clock and Hence its called ASYNCHROUS counter.
If your counter is cleared only after active edge of colck even reset is enabled, then it is called SYNCHROUS counter
In a similar...
hey, its very simple.
single &, | represent bitwise operators. while double & ,| ( ie && , || ) represents logical operators.
o/p of logical operators is a single bit. i.e. 1 (if true, non-zero) or 0 (if false , zero).
In ur case both "a" and "b" are non zero, hence the o/p is TRUE (in digital...
Re: interview question
Hi,
as per my knowledge........c==foo?a:b will be implemented as a ordinary mux while the other form is implemented as priority encoder. As there are only two states ( absence of elseif ) priority encoder is same as mux. Hence we will c no difference in simulator.
Hope...
Hi,
It depends. If capacture clock has positive skew with respect to launch clock then it aidsd hold time and may cause setup violations. Similarly if it has negative skew the hold violations may occur while hellping setup time
Thanks everone
"if u have 10% timing violation, use synthesis approach, if you have more , redesign the violated part may be good"
as said by funzero
is tht 10% with respect to total number of paths?
or somethingf else
hi,
As per my knowledge subtration and additon are both done in hardware itslef.Hence, 2's compilment should also be done in hardware.
Its quite easy to impelent tht. If u find it difficult to do tht plz let me know, i will help u out.
SantoshL
Thanks for the information David
Will u plz explian in brief all the alternatives u mentioned. and im in post layout stage so which is more appropriate choice for me?
Thanks and regards
santosh l
Hi, All
I'm a fresh college grad into industry as front end design engineer in design Center.
Im currently doing synthesis and STA.
What are the different techniques to fix timing violations........especially setup violations?
Hope u will help me
Thanks in advance
Santosh L
Yes, as said above hold violations are more critical.However we should fix setup violations in pre CTS ( CLOCK TREE SYNTHESIS) i.e. before P&R. Hold violations can be fix suitablly by inserting clock buffers in P&R stage.
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