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Recent content by santi001

  1. S

    Capless LDO design stability problem

    ldo and cap design difficult to comment without looking at the architecture. Also mention the load current.
  2. S

    stability of switched capacitor circuits

    Yes for every clock phase (different beta factor) you need to ensure stability.
  3. S

    Sigma delta adc stability verification

    adc stability Hi, I am working on sigma delta adc. Can anyone please tell me how to verify stability of sigma delta (1st order & 2nd order). Any link or ieee paper, thesis which has this info would be very helpful. Thanks
  4. S

    Sigma delta modulator - need explanation

    Re: sigma delta modulator Please someone clarify how the following equations are written.
  5. S

    Continuous time Bandpass Complex DeltaSigma ADC Simulation

    hi, I am new to the sigam delta. can you please help me wrt ABCD matrix. How to get ABCD matrix for 2nd order sigma delta modulator. I got the delta sigma tool box from https://www.mathworks.com/matlabcentral/fileexchange For a second order modulator the ABCD state space model is given as...
  6. S

    How to simulation drop out voltage of LDO

    simulation drop as a LDO spec you can define DC load regulation and transient load regulation. ( there are many other but wrt load these are main) I mean check output voltage when load current is 0 and when full load current, under DC conditions. This will give you the DC load regulation. Run...
  7. S

    Sigma delta modulator - need explanation

    sigma delta modulator Hi, I have a doubt about the modeling of sigma delta modulator. I am very new to this field. I got the delta sigma tool box from https://www.mathworks.com/matlabcentral/fileexchange For a second order modulator the ABCD state space model is given as A=[1 0; 1 1]...
  8. S

    Problem with a SAR ADC with 8 bit resolution

    ADC The ADC op will be 11001101. corresponding quant err = 801m-800.781mv < LSB. You need not consider the 11001100 case. If you get this output it means ADC is not ideal and there is any error. I think you have to consider "800.781mV" not "800.7mV"
  9. S

    Problem with a SAR ADC with 8 bit resolution

    ADC The 4mV argument comes only when your reference is 800mV. Basically it means for 8 bit with 1V reference, the rational numbers that you would worry are 796mV 800mV and 804mV. You dont care what what happens between them. in other words for 800mV reference from 798mv to 802mV (+/-2mV) if...
  10. S

    How to convert voltage -5V to +5V to a range of 0-5v

    When vin = 0. The gain of this amp is =(1+(R/2R)) = 1.5
  11. S

    basic question reagrding LDO design

    ldo design and calculation Your impedence which you measure is only at one frequency and the transient is effective response for a step input (which has all the frequencies). If you give a sin wave load of frequency equal to your UGB you will see the drop corresponding to the resistive impedence.
  12. S

    How to measure the jitter of PLL in cadence?

    PLL Jitter measurement Thanks to you all !!!
  13. S

    How to measure the jitter of PLL in cadence?

    PLL Jitter measurement Hi All, How to measure the jitter of PLL in cadence? Can anyone please help me? -:?:
  14. S

    SFDR problem for track and hold circuit

    In a -ve feedback circuit output should be some multiple of input. Everything else is error. Which will be reduced by (1+A(f)β) In freq domain this error will be reduced based on the gain of the OTA at that frequency. Higher gain at higher frequency => more UGB. On the other hand if over all...
  15. S

    SFDR problem for track and hold circuit

    Based on the window that you have used for fft. you will know which all bins belong to signal. If that is not right then signal power will be distributed all over the place. Then you can compare the signal power with next dominant harmonic within FS/2

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