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Recent content by santhosh.vlsi

  1. S

    Building Blocks!! Standard Cells

    Hi, 1) Can any one can emphasize on how quickly draw the layouts by referring the schematic. Only Eulers path is the better method ? 2) How to estimate Power bus width 3) How to self learn on skill scripting as its very useful for standard cell layouts(Good material)
  2. S

    Question regarding SRAM compilers

    Hello all, Please provide me the details about memory compiler(generator).As per my knowledge compiler generates the cut according to user specifications.What parameters we have to consider in cut generation, like how to consider MUX,WORD,BIT parameters.apart from these three parameters any...
  3. S

    Memory Layout Question

    Thank You Mr.erikl As per my knowledge technology node means it depends on the gate length of the transistor.Suppose i want to design a memory block in 22nm node, What points i want to consider.Any text books enriches these aspects with EDA tool examples. Thank you
  4. S

    Memory Layout Question

    Hi all, Anyone can please provide me the details about the memory layout engineer responsibilities in the semiconductor companies.
  5. S

    how to simulate the design of tanner EDA tool in other machine

    Hi, I have designed a 32 bit ripple carry adder in tanner tool in my personnel computer. I want to simulate the same design in my laptop.i.e..,I do not want to design again in other machine so how to take the designed file and simulate in another tool. please tell me the procedure 8-O8-O...
  6. S

    LTspice simulation problem

    Hi.. Use the following in your design. .options gmin=1e-10 abstol=1e-10 reltol=0.003 revart back if it works fine............. Thank you
  7. S

    SRAM SNM Simulation - Hspice

    Hi.. Find some materials on SNM.They may help .... Thank you
  8. S

    static timing analysis

    Hi read the timing closure chapter from the book "VLSI Physical Design from graph partitioning to timing closure" it may help you.....
  9. S

    help needed for SRAM design in cadence

    HI all I have face difficulty in designing of sram design using Negetive word line concept. any body please help me to proceed.any body have complete sram design ( scematic capture) in LT spice....?:???:
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