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oh ,yes,i think i have understand what's your mean,can you told me where can i find some paper for scoreboard ...these things, i have openvera's lrm ,there is not much things in it.
you means i can turn .vr files to .vrp files directly by vip license,these .vrp files are a vip? in this my old testbench must be very integrity,my old testbench ,i didn't add monitor ,self-checker,function coverage,did these must include?
and then ,how can i downlode vip license?
or can you...
if i need the vip license means i use the vip developed by synopsys,but now i want to write a vip by myself,what do you think i need do?thank you very much!
i have write a iic testbench based on vera ,the next step is write a VIP, but i think there is not many difference between them ,can somebody tell me something?
when i translate and edit my program ,it usually tell me my .vrh files exist many errors ,other files not exist any errors,how can this instance happen?
i have read language lrm,refer to openvera i feel better now .when i see the examples, i find their files are very oddness,many .v files not exist,so why can be in this way?
Which city are you in? I know SNPS has Shanghai & Beijing offices, anyway email support is available across world! Use Solvnet.synopsys.com also.
i am in hefei ,did you heard of it ?
which country are you come from?can we use qq or msn exchange ideas?because in this way cost a lot of time .
hi aji_vlsi:thank you very much!
i have find $VERA_HOME,but when i find it ,i feel they are very difficult ,the easiest one is pci,and when i see its readme ,it's compile step make me confused.
at first ,i want to write a verilog programe and use openvera to verificate it ,but when compile it...
thanks for your advice! i said my english is poor means i usually can't understand the language manual and some datum very good!
when i write a verification ,do i must define interface ,port and bind at first ?
Added after 4 minutes:
and when i compile, if i verification a program based on...
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