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Re: several questions about the comparator
Which process are you using for this design ? What is your Vdd ? I don't think there is any accurate calculation procedure you can use for this design. If you mention the necessary details its possible to give an idea on device sizing & resistor...
accumulation varactors
Multifingered device will reduce your gate resistance as well as the capacitance Cgs. So make sure you split it into the minimum number of fingers you need and nothing more. Adding more fingers will only reduce your Cgs more.
guard ring analog digital
If you are planning to submit a individual test structure for you VCO then you can afford to have separate digital and analog grounds. The reason why we try to have a separate digital ground is to ensure the switching noise from the digital cells don't travel into the...
hello OpAmp,
To configure the VPULSE as clock generator in LTSpice, do we need formula to get the right frequency or we try to simulate different values until we get the right output??[/quote
Comparator operates at its frequency specifications. If you are designing a comparator then it should...
sample and hold designs
Can you specifiy what is your Vdd ? Can you add a snapshot of the sample & hold circuit which you are designing.
Can you add little more details on what frequency your planning to operate your S&H ?
The input common mode range capability of your Sample & hold would...
Re: Help on Mixer isolation
I also agree with Wireless man. Conversion Loss 0f 6 dB means its conversion gain of -6 dB.
If you have time take a look into the datasheet published by Hititte Microwave Corporation. If you look into their Active Mixer Data Sheet, you will find their specfications...
This layout looks fine to me .. But i would suggest that your guard ring should cover the complete NMOS input pair. You have left it incomplete at the point where input pins are being routed to diff pair. The reason for putting a complete guard ring is for reducing substrate noise and sinking...
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