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Hi,
If I place low voltage fet in high voltage well, will that device be considered as high voltage as well ?
For example:
Let's consider 5 volt to be high volt in 28nm TSMC process. and 1.2V to be low volt.
Now if I place 1.2V pmos in 5V NWELL, will the voltage on nets connected to that...
Hi
I have placed IP marker in my IP blocks to recognize IP blocks.
There are DRCs which we don't want to flag in those IP blocks. Of course, first approach come to mind is to tell DRCs not to flag under IP marker. But that raises concern if someone places some other devices or routes over...
I do have purpose. I want to go through each DRC checks which are affected and determine if the change I am making still applies to that DRC check. If not, then I will have separate definition of M1 for that particular check. I have also encountered similar need previously in my work flow. I...
Yes that will show me if DRC change affected any violation count on my layout. What I am looking for is a list of DRC check names which are affected to the change I made. For example:
Metal1 = M1 OR M1_DUMMY
A = Metal1 AND Metal2
B = A OR Metal4
Check.1 { @ Metal space : this check will be...
Hi,
I want find out which DRC checks are affected if I change some thing in DRC deck.
For example:
Metal1 = M1 OR M1_dummy
Now I want to change it to
Metal1 = M1
If I make a single change like this in DRC deck, how do I know which DRC checks will be affected by this change ?
Thanks
Sam
Hi,
I am looking at 28nm DRC deck and for DFM rules, I see different sections like "Recommended" , "Guidelines" , "Analog" etc.
What is the difference between these sections ? Specifically what is the difference between "Recommended" and "Guidelines" ? I appreciate your insight on this...
Thank you for your response.
I can follow your recommendation if my DRC is dependent on voltage on NET. But my DRC is dependent on potential differnece between nets. The logic is as following.
Example :
If Potential Difference between two metal1 nets is >=3V then spacing is 3um and if...
Hi all,
Is there any way to make cadence virtuoso layout faster when using SHIFT + F on large layout ?
Once I open CHIP level layout, and press SHIFT + F to make everything visible, it takes lot of time to make everything visible because of large layout.
Is there any way we can make it...
Hi all,
Is there any way to code DRC for voltage dependant metal spacing DRC checks ?
I know there are tools available for this, like Calibre RealTIme etc. But without spending money on those additional tools, is there any way to do it using basic calibre tools? I have Calibre nmDRC
Given...
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