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Re: CLK in DCM
thanks ur verilog verrsion is working.But it needs to have the libarary unisim included in the verilog file .I don't know how to do that. I am trying with the VHDL code but even with the sane parameters it is not getting locked.so please help me regarding this
Re: what is the problem?
hi
why don't u try to use "generate" statement.
It works well in the process.
Added after 22 minutes:
otherwise U instantiate the components outside the process statement.Assign the signals in the process block.Use enable signal to select ur components. that will do.
simprim library
U have to compile ur simprim library that is available in ur xilinx directory in the VHDL folder (src) .since ur using modelsim SE u need to compile them in ur modelsim only.Once U r compiling is over u add it as library in ur project.(u need to map it).If u have any problems...
Re: CLK in DCM
I used the installation template for using the DCM.and I had the clock in the frequency range specified.Has anyone got the code thats working.
Re: simprim?
simprim is the simulation primitives library. U can find it in xilinx folder in your system.U compile it and add to ur project.
Added after 10 minutes:
U need to compile the simprim codes to have _info file .U'll have that in ur work library then.
clkx2 dcm
I have a problem with generating CLK2X(twice the frequency) in virtex II FPGA .I am using the on chip DCM.My problem is when I am simulating using modelsim,the signal is not getting locked.so I am not getting The output clock.could any one please help me with the configuration file...
Re: memory in FPGA
Yaa thanks I am using a virtex II block Ram .but still I want to know whether a super scalar fetch engine can be downloaded into FPGA or not .memory size is
two 144 by 128 memories ,sixteeen 16 by 64 memories and a 164 by 64 memory
I am implementing a cache memory in FPGA.
for that i need a memory of 16 bytes wide and 256 entries.
I am implementing using VHDL.
the problem is I want to download in FPGA.
Is there any way to make effective utilization of area in FPGA in this application
think u have got some xilinx documentation,if so just refer to the xst in software manuals .there it is given how to initialize rams or write into rams
Re: fpga - vhdl
Refer some basic coding techinques in VHDL before going for implementation
refer VHDL books such as VHDL primer by Bhaskar,VHDL programming by Douglas perry and search in internet for an implementable algorithm
project
I am implementing a Trace cache in VHDL (FPGA implementation) as my PG project.would it be good enough for it.
and if any one have material regarding its implementation please help me
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