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Recent content by sandy2811

  1. S

    ATPG Test Coverage for stuck@ and @speed

    Yeah surely, in stuck at as per it's name no speed dependency but in terms of fault covering which type of faults it will cover so coverage is more than transition.
  2. S

    ATPG Test Coverage for stuck@ and @speed

    Hi all, Why the test coverage is more for "stuck-at" as compared to "at-speed or transition pattern" in ATPG? and which type of fault is not covered in transition that will cover in stuck-at?
  3. S

    Input port and input output port declaration in top module

    Inout port and input output port declaration in top module Hi all, If i have three modules, one is top and other two is instaintiated in that top module. In top i have declare an inout port a and in other two modules i declared the same port as input a and output a. So is it correct way of...
  4. S

    Parallel Pattern Simulation

    This question is related to VCS simulator.
  5. S

    Parallel Pattern Simulation

    Hi, Can anybody explain the procedure of 1 parallel 5 serial pattern simulation. Is that any example or link or any whitepaper based on this serial and parallel simulation.
  6. S

    Unknown Clock Signal

    After reading this I understood the actual meaning of that always statement, Thanks, guys............ Sandy.
  7. S

    Unknown Clock Signal

    Ohhh right Klaus, I have edited that.
  8. S

    Unknown Clock Signal

    Hi, In my simple design, I am giving some inputs and it is difficult for me to know which signal act as a clock. i.e. only "y" act as a clock or both "x" and "y" act as clock. module my_design (q, d, x, y); input x, y, d; output reg q; always@(posedge x or posedge y) begin if(x) q <=...
  9. S

    Adding Shift Register in scan chain without converting to scan cell

    Is that any particular command in DFTAdvisor tool for doing the same as DC.
  10. S

    Adding Shift Register in scan chain without converting to scan cell

    I am doing scan insertition on DFTAdvisor tool. So in this tool how it is possible. - - - Updated - - - Hi oratie, As you said, DC will automatically identify existing shift registers and convert only first reg into scan equivalent. So other flops that are in shift register are also part of...
  11. S

    Fault category

    Please go through the scan atpg user guide. **broken link removed**
  12. S

    Adding Shift Register in scan chain without converting to scan cell

    Hi all, Is it good to convert shift register as scan cell in netlist or not ? But how to add shiftt register in scan chain without converting it to scan cell/flops. I have 4 bit shift reg in my design and i want to add this reg in scan chain without converting it to scan cell, but i am not...
  13. S

    Problem to understand internal architecture of JTAG

    I have read the spec, and I am not getting it correctly that in case of if I am passing an instruction then any data register is accessible according to that instruction but how the values are captured in data register. And I also willing to know about at which phase of DFT ,JTAG comes, i.e...
  14. S

    Problem to understand internal architecture of JTAG

    JTAG is defined as a serial communication protocol and a state machine accessible via a TAP. But how the data is captured in capture_IR or capture_DR state it is the main issue and the data is shifted out through mux on TDO but what are the control signals at that time.

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