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tie high cell
We used logic constants in the RTL, so there will have some internal nodes tie up to logic "H' or "L". Astro could use "Tie-High Cell"s or "Tie-Low Cell"s to make the connections.
Is there anyone could tell me reasons why we do NOT connect those signals directly to the Vdd /...
For the DFT issues, please keep the async. reset for all the flops. However, you would like to use sync ckts at the very input point to re-sync the async. reset-singal from another chip.
Currently the scan-insertion tools can fix the sync reset problem by gating the reset signal generated in...
difficult dft question
Memory BIST controller circuit might NOT need to be scaned, since the controller ckt failed.... then the BIST test fail.
You will catch the failure in the BIST test, why do you waste your gate count in scan?
static timing analyis
Hi,
1. If the violations are really small, just let it go!!! Since the best-best case and/or worst-worst case might not really happen... :)
2. Modified gate level netlist manually, and then do the ECO
3. Re-synthesis with modified constrains (step 2 is usually more...
For a chip of such size (5M gates), using an uncontrolable reset signal, you are generating a big hole for DFT.
Have you every thought of the mass-production issues?
Thank you guys.
With your suggestions, I think I am going to try following methods:
1. Do the RC extraction
2. Get setload (if Synopxxx still support that format)
3. Generate a fake SDC for the tool and then tune it later, since I need a real constrain for the STA anyway
Routing Power
If you access to the technology file, you can find the sheet resistance on each layer of the metal. Those numbers are different on each layer.
Picking the top layer of metal for the power truck, designers are considering the low resistance / low IR drop (the top layers are...
Hi, YaSon:
It there any place in the SDF included the timing check? As far as I know, SDF just included the net/cell delay in the number of time (best, typical, worst)
Isn't the timing ARCs check by the STA/simulation tools?
Reset pin
In Design compiler, most of the time, reset/clock will be put in "DONT TOUCH" for those high fanout nets, so the buffer insertion/sizing will NOT perform on those signals.
In the later phase of the design, backend tools will finish the buffer insertion/ buffer sizing according to...
25 -- > 18 -- > 13 -- > 09 --> 065
All the previous number is around 1.41 times of hte next number.
Does that trigger you any thoughts?? (hints: 1.41^2 = 2)
memory compiler
What's the technologies, foundries ... you are looking for? Some library providers have it. But you need to be qualified (registered, sign NDA...) before you down load the tools.
Please try Artisan, Faraday, VST, ....
Got a standard cell design's GDSII / netlist from an IP provider, I would like to generate SDF from A$tr0 (since the provider provided libraries, but not the SDF). However, the tool asked for the clock definations!!
I knew this is not a normal design flow to generate SDF. But I am wondering...
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