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Recent content by sandip_micro

  1. S

    Regarding VCO Layout and IR drop,EM

    Please answer this question: (Suppose u have to do layout of VCO and there are 4 satges of Differential type VCO stages1,2,3,4..How you will place these 4 VCO stages and while connecting one VCO stage to second VCO stagw,how will u connect?I mean to say what care u will take while connecting?)...
  2. S

    How to simulate or plot an eye diagram?

    ezwave examples U can see the eye diagram in cadence vy doing Transient simulation. After completing simulation go for the Special calculator. In Special Calculator one option is there by name Eye diagram. main thing is how to Interprit the Eyediaram. I am attaching one PDF along with this...
  3. S

    verilog a code for divide by n

    verilog divide by 10 Hello dear.. Its nice that u post the code here. I want to ask is this code be used in Charge Pump PLL for the Feedback Divider Block? Its like a Programmable Feedback divider..Am i right? Added after 1 minutes: assign out=(enable==1)?((dbn_en==0)? clk n[0]==1)...
  4. S

    current starved inverters for delay control

    I alos want the Material?can anyone please send?
  5. S

    How to design PFD in Charge Pump PLL?

    Heel Amaranath I want to know the general Design Procedure of PFD Block? May be i/p freq=100MHz Then how to start? Do u have any PDF which explains the design of PFD block?
  6. S

    How to simulate the jitter in ring oscillator using Spectre?

    Re: jitter simulation Dear We have to do two analysis to see the Phase Noise in Spectre.The two analysis are 1.PSS 2.Pnoise In specre simulation choose these two analysis and run the simulation. If u click on PSS u have to give some parameters.same is the case with Pnoise.
  7. S

    How to design PFD in Charge Pump PLL?

    Hello friends I want to ask whats the design procedure of Phase Frequenct Detector Block? In PFD block we saw 2 D Flip Flops and one AND gate. Input signals are: REf and fedback and RESET Output singals are : UP and DN If the VCO Freq=200 MHZ Input Freq Range=3 MHZ ~800 MHz
  8. S

    Simulation of a charge pump for a VCO for PLL

    You have to simulate the Charge Pump Ckt and plot the average output current of the charge pump (Icp)Vs phase difference(Phy) between the FREF and FEEDBACK .There are many lectures on CP.Best paper for CP is Voughan Rhee`s paper.
  9. S

    How to simulate pmos i-v curve with hspice ?

    pmos i v u will find this in Allen Hollberg book also.Its simple.U can plot Vds Vs Ids curve.
  10. S

    Transfer function of op amp....

    Even in John Martin book u find explanation about the opamp.
  11. S

    How can i design vco in 90nm?

    Hello dear.. i am also trying to design a Symmetrical type load Delay cell in 0.18u.Maneatis delay cell PDF u might have read.shall I send the link. http://www.truecircuits.com/images/pdfs/maneatis96b.pdf main thing is there is a design procedure for designing such tyle of Delay Cells. One more...
  12. S

    pll loop parameters calculation with matlab?

    I can tell u the book name. William F. Egan, Frequency Synthesis by Phase Lock (2nd ed.), John Wiley and Sons, 2000 (provides useful Matlab scripts for simulation
  13. S

    How to generate 4 bias voltage?

    I think Martins book is having a ckt which shows the cascode bias volatge generations and tail curent bias generationjs voltages
  14. S

    Would you give me a common case about PLL?

    Please refer the book VLSI for Wireless Communications by B.Leung.
  15. S

    Jitter measurement in PLL

    Please refer Cadence Tutorial on Jitter.It explains every type of Jutter types.Search in google..Just type Jitter,cadence..u will get.If u didnt get pleas tell me.I will give u the link.

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