Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by sandeep_torgal

  1. S

    Virtual connection and JoinNets

    Hi, Can anybody tell me what is the command for Virtual connection and JoinNets in Calibre lvs. Please point me to the file to be edited for this as am new to this flow. Regards, Sandeep
  2. S

    order of lvs checking

    FIrst connect all the unconnected signals from lvs report. Then check for the signal mismatches and device errors. Let me know the tool you are using for lvs so that i can elaborate more... Regards, Sandeep
  3. S

    the problem of well isolation

    Hi erikl, Do u mean that the diffusion are also connected to VSS in a MOSCAP since it will not let the parasatic diode to be forward biased. And the poly can be connected to the +ve voltage wrt the nwell. Correct me if am wrong. Regards, Sandeep
  4. S

    Why Shielding lines are connected to VSS not to VDD

    guard ring shielding+adc The topic is whether shielding lines should be connected to VSS or VDD. I guess everybody who are discussing this topic knows what is shielding and uses of it. Please add valuable and relevant comments to the topic so that the visitor to the topic is not disappointed...
  5. S

    Virtuoso layout parameterization

    Skill lang is required if you use cadence. But what am asking Deepak is a script that works for MAGIC tool. Or else let him post the available script which might help others in the forum. Regards, Sandeep
  6. S

    What happens when in inverter pmos is connected to gnd/vss and nmos to Vdd?

    Re: Related to Inverter Hi, Ok to add to this, I added a chain of source followers with same drive in 0.35u technology and simulated the netlist. The output voltage at the fourth stage is saturating at 1.6V and am unable to understand why is it so. The voltage should have been 1V or so at that...
  7. S

    What happens when in inverter pmos is connected to gnd/vss and nmos to Vdd?

    Re: Related to Inverter Hi, It will not work as a inverter but as a source follower. The output will not swing from Vdd to Gnd, but it will be Vdd-Vtn to Gnd+Vtp Regards, Sandeep
  8. S

    IC Layout in DSM Technologies

    ic layout matching Thanks for the info. What am wondering is does it really effect if I do a cross coupled matching with the devices shared. A1 B1 B2A2 <----Sa---->A1<--------------------Sb--------------------> <--------------------Sa-------------------->B1<----Sb---->...
  9. S

    [SOLVED] LVS Errors due to Dummy transistors

    Agree with erikl. It even helps designers to use the dummies for the design changes if they dont want to re-layout at the end stages. Regards, Sandeep
  10. S

    IC Layout in DSM Technologies

    ic dsm Am still not clear how STI effects sharing of transistors for matching. Can you provide us some more info and if any doc available. Regards, Sandeep
  11. S

    Virtuoso layout parameterization

    Please post the script. Let me check if the script works in MAGIC for such a silly problem... Regards, Sandeep
  12. S

    How to fix Density errors in DRC?

    converting laff to gdsii Let me reframe the que : Can anybody throw light as to how the gdsii information is used in pattern generation. What are the steps from gdsii to tape-out.
  13. S

    How to fix Density errors in DRC?

    fixing geometric drc with encounter Regarding the density violations am not able to make out what you intend to convey. Can you plz elaborate. laff is lisp archival file format. We can convert laff to gds and viceversa. gds is the final thing which will be sent to fab. Can somebody throw more...
  14. S

    Virtuoso layout parameterization

    Carl_chao has already got that information and has thanked everybody for that.We have diverted the topic to something else. What sense does it make to write "make pcell" now. Regards, Sandeep
  15. S

    How to fix Density errors in DRC?

    via density drc Empty space is never an issue in chip level as they always place dummy metals(through scripts) before the laff is sent to fab...

Part and Inventory Search

Back
Top