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Recent content by Samuel Jimenez

  1. S

    Mux Synchronizer on Verilog FPGA

    But the adc data stream is not ordered. I mean, with adc datastream that is not ordered, an async. FIFO with gray code counters would not work. Or are the gray code counters only responsible for handling the writing/reading pointers?
  2. S

    Mux Synchronizer on Verilog FPGA

    I changed to behavioral like so: Here's the Verilog Code: reg [16-1:2] a_a1_o, a_b3_o; reg a_b1_o, a_b3_o; reg a_mux_enable; reg [16-1:2] b_a1_o, b_b3_o; reg b_b1_o, b_b3_o; reg b_mux_enable; always @(posedge adc_clk_in) begin a_a1_o <= adc_dat_a_i[16-1:2]; b_a1_o <=...
  3. S

    Mux Synchronizer on Verilog FPGA

    Thank you, No, it's not. I'm just having trouble how to appropriately interconnect mux output to the instantiated modules: For ex, using your presented logic (not complete mux sync design - just an example): cdc_dff dff1( //.input(..) D //.clk(..) clk //.outout(wire) ); //then cdc_mux...
  4. S

    Mux Synchronizer on Verilog FPGA

    I need help implementing a mux synchronizer on Verilog. I have little knowledge of Verilog and need this design as soon as possible. Any help is appreciated tremendously!!
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