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Hi,
I am required to design a current DAC (64 unit element NMOS) that sinks the output of another current DAC (16 unit element PMOS). The smallest current output from the PMOS DAC is 6uA and the required step size in current from the NMOS DAC is 6uA/256. I am confused as to how to bias the DAC...
I am designing a PLL wherein a current mode DAC plays the role of fine tuning the output frequency. This current is integrated onto a capacitor. The DAC receives its controls from a 6 bit MASH modulator which are demultiplexed to 64 and re-timed with the help of an FF to control each unit...
Hi, I am building a control amplifier for a VCO. The output voltage of the amplifier will drive a sensing PMOS and a charging PMOS (in the VCO)of 6*12u/1 and 3*15/1.5 each. To compute the load capacitance on the amplifier, I ran a dc on the oscillator to find out the Cgs+Cgd+Cgb of the PMOS's...
Hi, in the image above (taken from Design of CMOS Analog Design Circuits by Razavi), a high gain amplifier is used to provide common mode sense and feeback by controlling the current through M3 and M4. The idea is that if both Vout1 and Vout2 rise, then Ve rises, and the current through M3 and...
Hi all,
I had a slight confusion about how a current source load influences the intrinsic gain of a MOS after seeing the images below.
In the first image, the gain is intuitive. The current source load exhibits an infinite output impedance so that the effective Zout is equal to r0. Here, using...
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