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Recent content by samg

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    Concurrent constructs in Verilog?

    Hi, I recently came across this question: Name 5 concurrent constructs in verilog? All I could come up with was: always blocks (because multiple always blocks operate in parallel). [whether assignments happen concurrently or not depends on whether they are blocking or non-blocking. So that...
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    Missing JESD parameters in Xilinx JESD204 IP Rx!!

    I am trying to figure out how to use and configure the Xilinx JESD204B IP (v3.1 and v7.1) Rx. I can only find the parameters - F, K, L, SCR and subclass mode as "writable" in the AXI lite register space for Rx. The other JESD parameters are present in the register space for Rx, but are...
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    Configuring JESD parameters in Xilinx JESD204

    I am trying to figure out how to use and configure the Xilinx JESD204B IP (v3.1 and v7.1). I can only find the parameters - F, K, L, SCR and subclass mode in the register space for Rx. How can I set the other JESD parameters? Or are they read from the ILA sequence and I am not expected to set...
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    Waveform of verilog "reg" inside a task in Vivado

    Hi, Is it possible to trace the contents of a reg ("reg" data type in verilog) variable used inside a verilog task in Vivado simulation output? I just want to see the changes in that reg.
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    [SOLVED] Register space addressing in Xilinx JESD204

    I am a beginner with both AXI and JESD204. The address for control registers in the JESD204 IP is supposed to be a 32bit address but Xilinx documentation mentions address offset as 12bit values like "0x008", "0x00C". Are we just supposed to add zeroes in front when using these addresses for...
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    Configuring JESD parameters in Xilinx JESD204 IP

    I am more of a beginner and I am trying to understand how to configure and use the Xilinx JESD204IP. Currently, I am using Vivado v2012.4 and the target is to interface a kintex 7 FPGA with an ADC that supports JESD204B. I am going through the example design and certain things don’t make sense...
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